In recent years, a demand for liquid crystal display panels and the like as flat panel displays has been growing rapidly. Compared to a CRT (Cathode Ray Tube), the liquid crystal display panels consume less power, and can be made smaller with ease. Therefore, the liquid crystal display panels have been widely used in televisions, mobile phones, portable game devices, in-vehicle navigation devices, and the like.
Furthermore, an organic EL (Electro Luminescence) display panel, which consumes even less power than the liquid crystal display panels, has been developed, and has already been put to practical use in some products.
Among these liquid crystal display panels and organic EL display panels, an active matrix type display panel that has fast response speed and that can perform multiple gradation display in a simple manner is widely used.
In the active matrix type display panel, generally, a plurality of pixels are arranged in a matrix, and thin film transistors (Thin Film Transistors, hereinafter referred to as “TFTs”) are provided in the respective pixels as switching elements.
A basic configuration of a TFT is described with reference to FIG. 5.
In FIG. 5, a configuration of the TFT is illustrated. FIG. 5(a) is a plan view showing the configuration of the TFT. FIG. 5(b) is a cross-sectional view along the line I-I in FIG. 5(a). FIG. 5(c) is a cross-sectional view along the line II-II in FIG. 5(a).
As shown in FIG. 5, on a glass substrate as an insulating substrate 110, a silicon oxide film, which is a base insulating film 111, is formed. On a TFT formation region on the base insulating film 111, a polysilicon film is formed as a semiconductor film 112.
On the base insulating film 111 and the semiconductor film 112, a silicon oxide film is formed as a gate insulating film 113. On the gate insulating film 113, a gate electrode 114 made of a metal is formed. The gate electrode 114 is formed so as to traverse the semiconductor film 112.
The semiconductor film 112 includes a pair of high concentration impurity regions (source region and drain region) 112a and 112b that are formed by implanting a p-type or n-type impurity using the gate electrode 114 as a mask.
Here, in a case of a reverse stagger type TFT, the locations of the gate electrode 114 and the semiconductor film 112 are reversed.
It has been known that in a TFT that includes the semiconductor film 112 made of a polysilicon film and the gate insulating film 113 made of a silicon oxide film as described above, if an impurity is not added to a channel region of the semiconductor film 112, a threshold voltage shifts in a negative direction.
To solve this problem, a method of controlling the threshold voltage by injecting a p-type impurity such as boron (B) into the entire semiconductor film 112 before forming the gate electrode 114 has been proposed.
The methods of injecting the p-type impurity into the semiconductor film 112 include an ion implantation method, an ion doping method, and a gas doping method, for example. In the ion implantation method, only ions of the desired element are implanted into the semiconductor film after performing mass separation. In the ion doping method, the mass separation is not performed, and the impurity is implanted into the semiconductor film by acceleration. The ion doping methods include a method in which a material gas such as diborane (B2H6) is excited by RF (Radio Frequency) power to generate boron ions and these boron ions are accelerated to energy of several keV to 100 keV to be implanted into the semiconductor film, for example. The gas doping methods include a method of forming an amorphous silicon film that contains boron (B) by mixing a diborane (B2H6) gas into a silane (SiH4) gas, which is the material gas, in forming amorphous silicon on the base insulating film by the plasma CVD (Chemical Vapor Deposition) method, for example.
In a driver circuit of the liquid crystal display panel or the organic EL display panel, a CMOS Complementary Metal Oxide Semiconductor) that includes a p-type TFT and an n-type TFT is widely used. When the CMOS is used, unless the threshold voltage is adjusted such that the p-type TFT and the n-type TFT are both turned off when the gate voltage is 0V, a leakage current occurs, which increases power consumption. Particularly, in the current circumstances in which reduction of power consumption is desired, the threshold voltage of the TFT needs to be reduced so as to minimize the driver voltage.
However, the current-voltage characteristics of the n-type TFT and the p-type TFT are different, and therefore, it is difficult to adjust the threshold voltage such that both the p-type TFT and the n-type TFT are turned off when the gate voltage is 0V. This issue is described below.
Generally, in the TFT, in order to secure a dielectric breakdown voltage of the gate insulating film 113, edges of the semiconductor film 112 are processed so as to be inclined as shown in FIG. 5(c). Therefore, when the p-type impurity is implanted by one of the methods described above, the surface density of the p-type impurity per unit area becomes lower in the slanted portions of the channel region than that of the p-type impurity per unit area in the central portion of the channel region.
As a result, as shown in FIG. 6, in the n-type TFT, the slanted portions form a parasitic transistor having a small channel width and a low threshold voltage. This causes the actual current that flows in the TFT to have combined characteristics of the characteristics of the planarized portion and the characteristics of the slanted portions, which exhibit two-step characteristics. On the other hand, in the p-type TFT, the characteristics of the slanted portions are masked by the characteristics of the planarized portion, and therefore, the characteristics of the slanted portions do not affect the threshold voltage. FIG. 6 is a graph showing the current-voltage (I-V) characteristics of the p-type TFT and the n-type TFT.
The current-voltage characteristics of the n-type TFT and the p-type TFT are described in more detail with reference to FIG. 4.
FIG. 4(a) shows the current-voltage (I-V) characteristics of the n-type TFT. FIG. 4(b) shows the current-voltage (I-V) characteristics of the p-type TFT.
As indicated by a solid line in the graph of FIG. 4(a), the n-type TFT is affected by the parasitic transistor of the slanted portions, causing the drain current to change in two steps when driving up near the gate voltage of 0V. On the other hand, the p-type TFT is not affected by the parasitic transistor because the characteristics of the slanted portions does not exceed the characteristics of the planarized portion, and therefore, as indicated by the solid line in the graph of FIG. 4(b), the drain current near the gate voltage of 0V changes in one step.
As described, the current-voltage characteristics of the n-type TFT and the p-type TFT are different from each other. When a CMOS is formed of the n-type TFT and the p-type TFT having these characteristics, it is difficult to control the injection amount of the p-type impurity such that both the p-type TFT and the n-type TFT are turned off when the gate voltage is 0V.
In order to solve this problem, Patent Document 1 describes a method of manufacturing a TFT substrate.
FIG. 7 is a cross-sectional view showing the method of manufacturing a TFT substrate described in Patent Document 1.
Below, an example of the method of manufacturing a TFT substrate is described with reference to FIG. 7. FIG. 7(a) shows a cross-sectional configuration of an n-type TFT formation region in the TFT substrate. FIG. 7(b) shows a cross-sectional configuration of a p-type TFT formation region in the TFT substrate.
As shown in FIGS. 7(a) and 7(b), first, on a glass substrate as an insulating substrate 241, a silicon oxide film, which is a base insulating film 242, is formed.
Next, on the base insulating film 242, an amorphous silicon film containing boron (B), which is a p-type impurity, is formed as an amorphous semiconductor film. Next, the entire upper surface of the insulating substrate 241 is irradiated with an excimer laser to crystallize the amorphous semiconductor film, thereby turning it into a crystalline semiconductor film 243. In other words, the amorphous silicon film is turned into a polysilicon film.
Then, a mask film 244 formed of a silicon oxide film, for example, is formed on the crystalline semiconductor film 243.
Next, using a positive type photoresist, a resist film (not shown in the figure) is formed on the mask film 244 in a TFT formation region.
Then, etching is performed so as to form the mask film 244 and the crystalline semiconductor film 243 into an island shape. Here, edges of the resist film are slanted such that the width of the resist film becomes narrower generally from the bottom portion toward the upper portion. The slanted portions are etched to recede gradually, which forms slanted portions in the edges of the crystalline semiconductor film 243.
Next, the resist film is removed by a removal liquid or plasma ashing.
Then, a resist film R4 is formed so as to cover the p-type TFT formation region completely (see FIG. 7(b)). Here, the resist film R4 is not formed in the n-type TFT formation region (see FIG. 7(a)).
Next, using an ion doping device, boron (B) is implanted into the entire crystalline semiconductor film 243 in the n-type TFT formation region by setting the conditions such that boron (B) passes through the mask film 244. At this time, boron (B) is not implanted into the p-type TFT formation region because it is covered by the resist film R4.
Next, after changing the conditions such that boron is blocked by the mask film 244, boron is implanted into the slanted portions of the crystalline semiconductor film 243 in the n-type TFT formation region. This way, in the n-type TFT formation region, the p-type impurity is selectively implanted only into the slanted portions of the crystalline semiconductor film 243, which are exposed from the mask film 244. This makes it possible to suppress the effects of the parasitic transistor in the slanted portions in the n-type TFT.
Then, the resist film R4 is removed, and a gate insulating film and a gate electrode are formed on the crystalline semiconductor film 243.